Ol mak bilong prodak
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PARAMETA |
SAPLAI VOLTEJ |
OL TOKTOK |
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1.8V |
2.5V |
2.8/ 3.0/ 3.3V |
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Frekwensi ranj |
10 ~ 52MHz |
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Frekwensi tolerans |
±1.0ppm |
Namba wan tol. @+25 digri |
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Stebiliti bilong frikwensi |
±0.5ppm; ±1.0ppm; 1.5ppm; ±2.0ppm; ±2.5ppm |
Lukim toksave aninit long tebol |
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Tempereja bilong wok |
–20 i go long +70 digri / –30 i go long +85 digri / –40 i go long +85 digri |
Long kombinesen bilong ol stebiliti antap. |
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Lapun long wanwan yia |
±1.0ppm |
@+25 digri |
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Autput wevfom |
Klipim Sine Wave |
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Autput lod |
10kΩ/10pF |
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Autput voltej level |
0.8Vp-p |
Minimum |
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Nois bilong hap (eksampel 19.2MHz) |
-115dBc/Hz/-135dBc/Hz/-148dBc/Hz |
@100Hz / 1kHz / 10kHz |
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Phase jitter RMS |
<1ps |
12kHz Liklik o wankain olsem Fj Liklik o wankain olsem 20MHz |
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Saplaim karent |
1.5mA/2.0mA |
@10kΩ/10pF (higher value>26MHz) |
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Tok save:Frekwensi stebiliti em i frikwensi deviesen antap long tempereja reinj long +25 digri |
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Ol samting bilong prodak
■ Liklik 2.0x1.6x0.8 wantaim 4-pela 'solder pad'
■ Ol strongpela stebiliti antap long tempereja reinj
■ RoHS kompliant, LEAD-FREE, HALOGEN-FREE na REACH kompliant
Ol aplikesen
- Low Power Quartz Oscillator TCXO 2016 TC21S4 series em ol i save yusim planti long: WiMAX / WLAN / Ethernet, Mobil aplikesen, Telekomyunikesen na ol narapela prodak.
Ol gutpela samting bilong prodak
Isi plesmen
Tep na ril i bihainim ol standet bilong EIA-481, na dispela i mekim isi long putim long masin.
Liklik sais na bikpela stebiliti
Liklik 2.0x1.6x0.8, ± 2.5ppm 'frequency stability'.
setifiket
Low Power Quartz Oscillator TCXO 2016 Series i gat RoHS/REACH-setifiket, i no gat lid-, na i no gat halogen-.
FAQ
Q1: Hamas em i namba bilong liklik paket bilong Suzhou Hangjing's Low Power Quartz Oscillator TCXO 2016?
A: 3000pcs/Reel.
Q2: Wanem ol spesifik dimensen na pin definisen bilong 2016 paket? Em i ken wok wantaim ol narapela paket?
A: 2016 paket i tok long 2.0mm×1.6mm× (planti taim 0.8mm tik), na tu namba bilong ol pin (olsem 4-pela pin) na ol wok mining (olsem, pawa, graun, autput, enable) i stret wantaim disain i stap pinis, na sapos ol i mas senisim 'circuit layout'.
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